1. Field of the Invention
The present invention relates to computer systems and, more particularly, to a data bus for isochronous data within computer systems.
2. Description of the Related Art
Computer systems, such as personal computer systems, were originally developed for business applications such as word processing, databases and spread sheets, among others. Computer systems, however, are currently being used to handle a number of isochronous tasks including: multimedia applications having video and audio components, video capture and playback, telephony applications, and speech recognition and synthesis, among others. Generally speaking, isochronous tasks are time-dependent tasks. In other words, the data handled by an isochronous task must be delivered or processed within certain time constraints.
One problem that has arisen is that computer systems originally designed for business applications are not well suited to the time-dependent requirements of modern multimedia applications. For example, modern computer system architectures still presume that the majority of applications executed are business applications, such as word processing or spread sheet applications. Typical computer systems are inefficient at handling streams of time-dependent data, or isochronous data, that make up multimedia data types. The isochronous data of multimedia tasks require the maintenance of a temporal component. For example, audio signals are coded as a stream of samples taken at a consistent sampling rate. The temporal relationship between these samples must be maintained to prevent perceptible errors such as gaps or altered frequencies. Likewise, the loss of the temporal relationship in a video signal can cause blank screens or lines.
The bus structures in typical computer systems are not designed to handle isochronous data. Bus contention, delays and overhead prevent buses, such as the Peripheral Component Interconnect (PCI) bus, from reliably transferring data at precise intervals as required for isochronous data.
Several data bus protocols have been developed to facilitate the transfer of isochronous data within computer systems. These standards include the I2S bus defined by Philips and the Audio Codec ""97 (AC ""97) bus defined by Intel. To reduce cost, these buses are serial buses rather than parallel buses. Unfortunately, these serial buses do not efficiently support multiple data streams with different sample rates. This is especially true when there is no clear relationship between the sample rates of the various data streams (e.g., where the sample rates of the data streams are not multiples or divisors of each other). One method of combining data streams having different sampling rates is to convert the data to a common sample rate. This conversion may be performed by using interpolation and/or decimation. Unfortunately, data conversion is a time consuming and hardware intensive task. Further, to convert the data back to the original sample rate, requires information identifying the original sample rate to be transmitted with the data.
A further shortcoming of conventional buses for transmitting isochronous data is the inability to detect and compensate for clock drift between sample clocks within the computer system. Techniques for compensating for clock drift include phase-lock loop techniques and interpolation. Unfortunately, these techniques are hardware intensive and/or time consuming.
What is desired is an isochronous bus that efficiently handles multiple isochronous data streams with different, non-related sample rates. It is further desirable to detect and correct clock drift between multiple clocks within the computer system.
The problems outlined above are in large part solved by an isochronous data bus in accordance with the present invention. The isochronous bus may include four signals: a data signal, a data valid signal, a frame synch signal and a clock signal. The bandwidth of the data signal is partitioned into a plurality of frames. The frame rate may be selected based upon the sample rate of one of the isochronous devices connected to the isochronous bus or maybe some divisor of the data rate of the isochronous bus. Each frame is partitioned into a plurality of data channels. Each data channel transmits data from an isochronous device. A number of bit time slots are allocated to each data channel. The number of bit time slots allocated to each data channel varies based upon the sample rate of the device corresponding to the data channel. For example, assume a computer system has a first device with twice the sample rate of a second device. A first data channel corresponding to the first device will have twice as many bit time slots allocated per frame as a second data channel corresponding to the second device. In one embodiment, each data channel is allocated more bit time slots than the nominal samples of its corresponding device. In this manner, any drift of the sample clock may be accommodated.
A data valid signal is transmitted synchronous to the data signal and the clock signal. The data valid signal indicates which bit time slots include valid data. As discussed above, a data channel may be allocated more bit time slots than the expected number of samples during a frame. The data valid signal is asserted during each bit time slot that represents valid data. The data valid signal is unasserted during bit time slots which are not utilized during that frame.
The drift of the sample clock of a device relative to the isochronous bus clock may be detected by monitoring the period of the data valid signal. If the period of the data valid signal increases over time, the sample rate of the device leads the isochronous bus clock. Alternatively, if the period of the data valid signal decreases over time, the sample rate of the device lags the isochronous bus clock. In one embodiment, the period of the data valid signal for a data channel is integrated to determine the lead or lag of the sample clock of a device relative to the isochronous bus clock. In one particular embodiment, the lead or lag information is provided to the device, which adjusts its sample rate to synchronize its sample clock with the isochronous bus clock.
Broadly speaking the present invention contemplates a method of transferring time-dependent data of a plurality of devices wherein the data of the plurality of devices have independent sample rates, comprising: partitioning a bus bandwidth into a plurality of frames; partitioning a first of the plurality of frames into a plurality of data channels corresponding to the plurality of devices; allocating a number of bit time slots to a first of the plurality of data channels, wherein the number of bit time slots is at least equal to a nominal number of data samples of a device corresponding to the first data channel during a period of the frame; generating a data valid signal that identifies which bit time slots represent valid samples; determining a lead or lag of a clock of a first of the plurality of devices relative to a data clock by calculating a change of a period of the data valid signal, wherein the change of the period of the data valid signal identifies a number of samples in a first frame relative to a number of samples in a second frame.
The present invention further contemplates an apparatus for transmitting or receiving isochronous data from a plurality of isochronous devices with independent samples rates, including: a plurality of isochronous devices, an isochronous data port coupled to the isochronous devices, and an isochronous bus coupled to the isochronous data port. The isochronous data port includes a lead/lag indicator configured to determine a rate of a clock of a first of the plurality of devices relative to a data clock. The isochronous data port is configured to acquire data from the plurality of isochronous devices and to output frames of time-dependent data on the isochronous data bus. The first frame is partitioned into a plurality of data channels corresponding to the plurality of isochronous devices. The first of the plurality of data channels corresponding to a first of the plurality of isochronous devices is partitioned into a plurality of bit time slots, wherein a number of bit time slots allocated to the first data channel is at least equal to a number of samples from the first isochronous device during a period of the first frame.
The present invention still further contemplates a computer system including: a processor, a memory coupled to the processor, a plurality of isochronous devices, an isochronous data port coupled between the isochronous devices and the memory, and an isochronous bus coupled to the isochronous data port. The isochronous data port includes a lead/lag indicator configured to determine a rate of a clock of a first of the plurality of devices relative to a data clock. The isochronous data port is configured to acquire data from the plurality of isochronous devices and to output frames of time-dependent data on the isochronous data bus. The first frame is partitioned into a plurality of data channels corresponding to the plurality of isochronous devices. The first of the plurality of data channels corresponding to a first of the plurality of isochronous devices is partitioned into a plurality of bit time slots, wherein a number of bit time slots allocated to the first data channel is at least equal to a number of samples from the first isochronous device during a period of the first frame.